Engineering Reference
PCB Materials, Stackup and Controlled-Impedance Terms Reference
Lookup PCB Dk, Df, core, prepreg, copper roughness, stackup, microstrip, stripline and differential-pair terms with controlled-impedance modeling boundaries.
Material and Stackup Terms
| Term | Meaning | Boundary |
|---|---|---|
| Dk / εr | Relative permittivity used by the selected field model | Depends on frequency, resin content, weave, direction and test method |
| Design Dk | Effective value selected for an impedance-design workflow | May differ from laminate datasheet nominal Dk |
| Df / loss tangent | Dielectric-loss indicator at stated frequency and method | Not a complete insertion-loss model |
| Core | Cured laminate with copper on one or both sides | Finished thickness and properties depend on construction |
| Prepreg | Partially cured resin/glass bonding layer | Pressed thickness depends on glass style, resin and copper pattern |
| Copper roughness | Conductor surface profile | Can increase high-frequency loss and alter effective geometry |
| Solder mask | Coating over outer-layer traces | Changes dielectric loading and impedance |
| Glass weave | Woven reinforcement structure | Local Dk variation can affect skew and impedance |
Controlled-Impedance Terms
| Term | Meaning | Boundary |
|---|---|---|
| Microstrip | Outer-layer trace referenced mainly to one adjacent plane | Fields occupy dielectric and air/mask regions |
| Stripline | Trace embedded between reference planes | Fields are primarily confined in dielectric |
| Single-ended impedance Z0 | Characteristic impedance of one conductor to its reference | Depends on finished geometry and material model |
| Differential impedance Zdiff | Odd-mode pair impedance between coupled traces | Not always exactly 2 × Z0 because coupling matters |
| Trace width W | Finished conductor width | Etch compensation and trapezoidal sidewalls affect effective width |
| Dielectric height H | Trace-to-reference-plane separation | Use finished stackup dimension, not board thickness |
| Pair spacing S | Model-defined separation between traces | Confirm edge-to-edge versus center-to-center convention |
| Copper thickness T | Finished conductor thickness | Base plus plated copper can differ by layer |
Single-Ended Example
The canonical model estimates 71.18 Ω for W=0.15 mm, H=0.18 mm, T=35 µm and Dk=4.2 microstrip.
Differential Example
At 0.15 mm spacing, the model estimates 111.66 Ω differential and 21.57% coupling.
Fabrication Handoff
Specify target impedance and tolerance, layer/reference geometry, spacing convention, copper treatment, mask state and material family. Let the fabricator return a manufacturable finished stackup and compensated width, then verify with field solving and coupons where required.
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FAQ
What is PCB dielectric constant?
Dk is a material-model input whose useful design value depends on frequency, construction, direction and test method.
Is FR-4 Dk always 4.2?
No. FR-4 covers many materials. Obtain design Dk from the selected laminate and fabricator stackup.
What is the difference between core and prepreg?
Core is cured laminate; prepreg is a bonding dielectric whose pressed thickness depends on construction and copper pattern.
What is the difference between microstrip and stripline?
Microstrip is an outer-layer line in mixed media; stripline is embedded between reference planes.
Is differential impedance exactly twice single-ended impedance?
Only when coupling is negligible. Pair spacing changes odd-mode and differential impedance.
Does solder mask affect impedance?
Yes. It adds dielectric loading to outer-layer traces.
Why does copper roughness matter?
At high frequency it can increase conductor loss and alter effective electrical geometry.
Can a closed-form calculator replace a field solver?
No. Use it for early estimates, then verify the finished stackup with the fabricator or a field solver.