Engineering Guide · PCB
PCB Controlled Impedance: Microstrip, Stripline, and Differential Pairs
Design controlled-impedance PCB traces using microstrip, stripline, differential-pair geometry, stackup data, dielectric assumptions, and fabrication limits.
Updated September 24, 2026 · Intermediate · 18 min read
From PCB Geometry to Controlled Impedance
Controlled-impedance design connects an electrical target to a manufacturable PCB stackup. The target comes from an interface or system requirement; the board implementation comes from trace width, copper thickness, dielectric height, relative permittivity, reference planes, and, for differential pairs, spacing and coupling.
A PCB trace needs transmission-line treatment when its propagation delay is significant relative to signal transition time and the resulting reflections matter. That decision cannot be reduced to one universal clock-frequency threshold. Once distributed behavior matters, characteristic impedance Z0 becomes distinct from DC trace resistance.
This guide follows the exact closed-form approximations used by the ECParts PCB impedance calculators. It focuses on geometry, stackup, design iteration, and fabrication handoff. Reflection coefficient, VSWR, return loss, matching networks, quarter-wave sections, and general electrical-length theory remain with the RF Impedance Matching Guide.
Controlled-Impedance Workflow
| Step | Decision | Engineering Action |
|---|---|---|
| 1 | Obtain the target | Use the interface, device, or system specification. Do not assume every single-ended trace is 50 Ω or every differential pair is 100 Ω. |
| 2 | Choose the structure | Identify an outer-layer microstrip or an embedded stripline and its continuous reference plane or planes. |
| 3 | Use an actual stackup | Collect finished trace width, finished copper thickness, dielectric height, and a defensible relative-permittivity assumption. |
| 4 | Estimate single-ended Z0 | Apply the calculator model that matches the selected geometry; do not exchange microstrip and stripline equations. |
| 5 | Add differential coupling | For a pair, include the calculator spacing input and the coupling term rather than assuming Zdiff = 2Z0. |
| 6 | Explore sensitivity | Change width, height, spacing, copper thickness, and Er one at a time while remaining inside the approximation's useful range. |
| 7 | Review fabrication | Confirm material, finished copper, etch compensation, minimum geometry, and controlled-impedance capability with the fabricator. |
| 8 | Verify the final stackup | Recalculate with the released stackup and use fabricator modeling or a field solver when tolerance or geometry demands it. |
Geometry and Output Definitions
| Symbol | Meaning | Practical Interpretation |
|---|---|---|
| W | Finished trace width | Narrower or wider copper changes characteristic impedance and must reflect etching, not only nominal CAD width. |
| H | Dielectric height used by the selected model | It is the trace-to-reference geometry represented by the calculator, not total board thickness. |
| T | Finished copper thickness | The current ECParts approximations include T in the logarithm denominator. |
| Er | Relative dielectric constant | Use a value appropriate to material, construction, frequency, resin content, and the source test method. |
| S | Differential-pair spacing input | The current calculator consumes S directly in S/H. Its UI does not declare edge-to-edge versus center-to-center, so do not transfer geometry from another tool without confirming the convention. |
| Z0 | Single-ended characteristic impedance | This is a wave quantity of the modeled structure, not the trace's DC resistance. |
| Zdiff | Differential characteristic impedance estimate | The current calculator derives this from single-ended Z0 and an empirical spacing-dependent coupling factor. |
ECParts Microstrip and Stripline Models
The calculators use natural logarithms and SI dimensions internally. Because every geometric term appears as a ratio, consistent dimensions such as mm, mil, or µm give the same result after conversion. The logarithm argument must exceed one, and the calculator rejects geometry outside the useful range of its approximation.
Formula reference
Microstrip approximation used by ECParts
Z0 = [87 / √(Er + 1.41)] × ln[5.98H / (0.8W + T)]εeff = (Er + 1)/2 + [(Er - 1)/2] / √(1 + 12H/W)v = c / √εeffVariable definitions
- W
- trace width
- H
- dielectric height
- T
- copper thickness
- Er
- relative dielectric constant
- εeff
- effective dielectric constant
- v
- propagation velocity
Formula reference
Stripline approximation used by ECParts
Z0 = (60 / √Er) × ln[4H / (0.67π(W + T))]εeff = Erv = c / √ErVariable definitions
- The adopted implementation is a symmetric stripline-style closed-form estimate.
- Do not reuse microstrip H or effective-permittivity assumptions without matching the physical stackup.
| Property | Microstrip | Stripline |
|---|---|---|
| Conductor location | Outer layer above a primary reference plane | Embedded between reference planes in the adopted symmetric approximation |
| Field distribution | Partly in dielectric and partly in surrounding medium | More strongly confined within dielectric |
| Dielectric treatment | Uses calculated effective permittivity | Uses Er directly in the current model |
| ECParts Z0 coefficient | 87 / √(Er + 1.41) | 60 / √Er |
| ECParts logarithm | ln[5.98H / (0.8W + T)] | ln[4H / (0.67π(W + T))] |
| Implementation warning | Solder mask and external environment can shift the result | Plane spacing and conductor centering must match the model |
Differential-Pair Coupling
A coupled pair does not generally have differential impedance equal to exactly twice the isolated single-ended impedance. The ECParts calculator first evaluates the appropriate microstrip or stripline Z0, then applies a structure-specific coupling factor based on S/H.
Formula reference
Differential-pair approximation used by ECParts
Microstrip: K = 0.48e^(-0.96S/H)Stripline: K = 0.347e^(-2.9S/H)Zdiff = 2Z0(1 - K)Variable definitions
- K
- empirical coupling factor
- S
- calculator trace-spacing input
- H
- dielectric height input
- Z0
- single-ended baseline from the selected structure
- Zdiff
- differential impedance estimate
As S/H grows, K approaches zero and Zdiff approaches 2Z0. Smaller S/H increases the modeled coupling and moves Zdiff farther below 2Z0. The current calculator does not expose odd-mode, even-mode, or common-mode impedance as separate outputs.
Spacing convention boundary: the implementation labels S as “Trace spacing S” and uses it directly, but does not encode whether an external drawing should interpret it as edge-to-edge or center-to-center. Treat it as a model-specific input, document the convention in the design, and confirm the geometry with the fabricator or field-solver workflow.
Stackup and Fabrication Reality
A calculator can explore geometry, but the fabricator controls available laminates, pressed dielectric thickness, finished copper, etch compensation, and process capability. Controlled impedance is therefore a specification-and-feedback process rather than a one-time equation.
| Variable | Why It Moves | Design Action |
|---|---|---|
| Trace width | Etch removes copper laterally and the finished width may differ from the design value. | Ask whether the fabricator adjusts artwork for impedance. |
| Copper thickness | Base copper plus plating can change finished thickness and sidewall shape. | Use finished copper assumptions rather than copper-weight shorthand alone. |
| Dielectric height | Pressed thickness and laminate construction vary by stackup and process. | Use the released stackup, not generic board thickness. |
| Dk / Er | Nominal datasheet values depend on method, frequency, resin content, and glass construction. | Use the fabricator's modeling value where available. |
| Pair spacing | Etch variation changes coupling as well as individual trace impedance. | State the spacing convention and tolerance explicitly. |
| Discontinuities | Vias, pads, connectors, neck-downs, plane changes, and reference gaps are outside the uniform-line equations. | Review transitions separately and preserve return paths. |
Keep a continuous reference plane beneath or around the line. Plane splits, return-path gaps, vias, connectors, and layer transitions create discontinuities that these uniform-line formulas do not calculate. A line can meet its nominal cross-section target and still perform poorly at a discontinuity.
Worked Examples
Example 1: Microstrip Geometry Estimate
- Given: W = 0.15 mm, H = 0.18 mm, T = 0.035 mm, and Er = 4.2.
- Model argument: 5.98 × 0.18 / (0.8 × 0.15 + 0.035) = 6.944516.
- Z0 = 87 / √(4.2 + 1.41) × ln(6.944516) = 71.184 Ω.
- εeff = (4.2 + 1)/2 + [(4.2 - 1)/2]/√(1 + 12 × 0.18/0.15) = 3.00772.
- Propagation velocity = c/√εeff = 1.72863 × 10^8 m/s.
- Interpretation: this is a first-pass geometry estimate, not a fabrication guarantee or a DC-resistance result.
Example 2: The Same Numbers in the Stripline Model
- Given: W = 0.15 mm, H = 0.18 mm, T = 0.035 mm, and Er = 4.2, now selecting stripline.
- Model argument: 4 × 0.18 / [0.67π(0.15 + 0.035)] = 1.848997.
- Z0 = 60/√4.2 × ln(1.848997) = 17.995 Ω.
- The current stripline model uses εeff = Er = 4.2, giving v = 1.46284 × 10^8 m/s.
- Interpretation: identical numeric W, H, T, and Er do not describe electrically interchangeable structures. H and reference-plane geometry must match the selected model.
Example 3: Coupled Microstrip Differential Pair
- Given: the Example 1 microstrip plus S = 0.15 mm using the calculator's spacing input.
- Single-ended baseline: Z0 = 71.184 Ω.
- Coupling factor: K = 0.48e^(-0.96S/H) = 0.215678, or 21.568%.
- Zdiff = 2Z0(1 - K) = 111.662 Ω.
- This differs from 2Z0 = 142.368 Ω because the pair is coupled in the adopted approximation.
- Interpretation: spacing materially changes the result. Confirm whether a fabrication or field-solver workflow defines spacing the same way before transferring this geometry.
Example 4: Unit and Geometry Iteration
- The Example 1 dimensions are 5.9055 mil, 7.0866 mil, and 1.3780 mil because 1 mil = 0.0254 mm.
- Entering either unit set returns the same estimate because the calculator converts all dimensions to meters before applying ratios.
- Within this model's valid region, increasing W while holding H, T, and Er fixed lowers the calculated Z0.
- Use this directional behavior to approach a target, then rerun with the fabricator's actual stackup and finished dimensions.
Practical Limitations
- The formulas are closed-form approximations for early stackup exploration and sanity checking.
- The microstrip and stripline equations are the equations implemented by ECParts; this guide does not assign an IPC, Wheeler, or Hammerstad label that the source code does not establish.
- The model includes finite copper thickness through T but does not model trapezoidal etch profiles.
- Microstrip effective permittivity is estimated; the model does not calculate broadband dielectric dispersion.
- The calculators do not model dielectric loss, conductor loss, skin effect, copper roughness, or total insertion loss.
- Solder mask, glass weave, material anisotropy, resin content, and local copper environment are not explicitly modeled.
- The differential formula is an empirical coupling approximation, not an odd/even-mode field solution.
- The current UI calls S trace spacing but does not formally state edge-to-edge or center-to-center; treat S as model-specific until the convention is documented.
- Uniform-line formulas do not model vias, pads, connectors, neck-downs, plane splits, reference changes, or return-path discontinuities.
- Use a 2D/3D field solver or fabricator impedance service for tight tolerances, complex stackups, unusual geometries, or very high-speed channels.
Common Mistakes
- Confusing characteristic impedance with DC trace resistance.
- Using the microstrip equation for an embedded stripline, or vice versa.
- Using total PCB thickness where the calculator expects dielectric height to the reference structure.
- Assuming every single-ended trace should be 50 Ω or every differential pair should be 100 Ω.
- Assuming differential impedance always equals twice the isolated single-ended impedance.
- Moving spacing values between tools without checking edge-to-edge versus center-to-center definitions.
- Using a nominal laminate Dk as an exact broadband design value.
- Ignoring finished copper, etch compensation, dielectric tolerance, and the fabricator's available stackups.
- Treating controlled-impedance spacing as electrical-safety clearance or creepage.
- Treating a closed-form calculator result as a fabrication or compliance guarantee.
Engineering Boundaries
The calculators do not use frequency as an input and do not predict dielectric dispersion, loss tangent, skin effect, copper roughness, or total channel insertion loss. They estimate characteristic impedance and, for the single-ended tool, idealized propagation velocity and delay.
Controlled-impedance spacing is not a substitute for creepage or clearance. Safety spacing depends on working voltage, insulation type, pollution degree, material group, altitude, and the applicable requirements. Those topics remain reserved for a dedicated PCB safety-spacing reference.
For tight impedance tolerance, unusual geometry, asymmetric stackups, broad frequency ranges, or critical high-speed channels, verify with a 2D/3D field solver, fabricator impedance modeling, test coupons, and measurements on the finished construction.
Related Calculators
Calculator
PCB Microstrip / Stripline Impedance Calculator
Estimate Z0, effective dielectric constant, propagation velocity, and delay from PCB geometry.
Calculator
PCB Differential Pair Impedance Calculator
Estimate single-ended impedance, differential impedance, and spacing-dependent coupling.
Calculator
PCB Copper Thickness Calculator
Convert copper weight and finished-thickness units used during stackup review.
Calculator
Transmission Line Calculator
Evaluate electrical length, delay, and guided wavelength after line geometry is established.
Related Engineering Guides
Engineering Guide
RF Impedance Matching, VSWR, and Transmission Line Design
Continue from PCB geometry into mismatch, return loss, electrical length, and matching.
Engineering Guide
PCB Trace Width, Current Capacity and Temperature Rise
Review the distinct DC resistance, current, voltage-drop, and thermal design workflow.
Support reference
FAQ
What is controlled impedance on a PCB?
Controlled impedance is a design and fabrication process in which trace geometry, reference planes, dielectric construction, and manufacturing controls are selected so a transmission line meets a specified characteristic-impedance range.
What is the difference between microstrip and stripline?
A microstrip is generally an outer-layer conductor referenced primarily to a plane, with fields in both dielectric and the surrounding medium. A stripline is embedded between reference planes, so its field confinement and impedance equation differ.
Is PCB trace impedance the same as DC resistance?
No. DC resistance describes conductor loss from resistivity, length, and cross-sectional area. Characteristic impedance describes the voltage-to-current relationship of a traveling wave in a transmission-line geometry.
What determines microstrip impedance?
In the ECParts approximation, trace width W, dielectric height H, copper thickness T, and relative dielectric constant Er determine Z0. Real boards also involve solder mask, copper profile, roughness, frequency-dependent material behavior, and fabrication tolerances.
What determines differential pair impedance?
The current calculator starts with single-ended Z0 and applies a spacing-to-height coupling factor. Width, dielectric height, copper thickness, Er, structure type, and spacing input all affect the estimate.
Is differential impedance always twice single-ended impedance?
No. It approaches 2Z0 only when coupling is weak in the adopted model. Closer coupling changes the differential impedance, so spacing cannot be ignored.
Does pair spacing affect differential impedance?
Yes. The ECParts model uses S/H in an exponential coupling term. Because spacing conventions differ among tools, confirm whether the source geometry is expressed using the same definition before comparing results.
Should every PCB trace be 50 ohms?
No. The target comes from the interface, device, connector, cable, or system specification. Many digital and differential interfaces use targets other than 50 Ω.
When does a PCB trace need transmission-line treatment?
It depends on signal transition time, interconnect delay, trace length, return path, and acceptable reflection. Clock frequency alone is not a universal threshold; edge rate and physical implementation matter.
Why can the PCB fabricator change the final trace width?
A fabricator may compensate artwork for etching, finished copper, dielectric construction, and the impedance target. The released stackup and process model can therefore require a different width from an early calculator estimate.
When should I use a field solver?
Use a field solver or fabricator impedance service for tight tolerances, complex or asymmetric stackups, solder-mask effects, unusual copper profiles, high-speed transitions, anisotropic materials, or geometries outside the closed-form approximation's useful range.
Are controlled-impedance spacing and safety clearance the same?
No. Pair spacing controls electromagnetic coupling in a signal structure. Clearance and creepage address insulation and safety constraints involving voltage, environment, material, altitude, and applicable standards.
Disclaimer
These closed-form equations provide first-pass engineering estimates. Confirm critical controlled-impedance designs with the released fabrication stackup, material data, field solving or fabricator modeling, impedance coupons where appropriate, and measurements on finished hardware.