Engineering Reference
Logic Families and Voltage Levels Reference
Quick-reference digital logic voltage levels, VOH, VOL, VIH, VIL, noise margins, undefined regions, loading, family terminology, and mixed-voltage interface checks.
- Reading Time
- 13 min
- Format
- Threshold lookup
- Updated
- September 26, 2026
Static Compatibility Checklist
| Check | Pass condition | What it proves | What it does not prove |
|---|---|---|---|
| HIGH threshold | VOH,min ≥ VIH,min | Guaranteed HIGH recognition | Input safety, edge timing, or fan-out |
| LOW threshold | VOL,max ≤ VIL,max | Guaranteed LOW recognition | Sink-current or ground-shift margin |
| HIGH margin | NMH = VOH,min − VIH,min > 0 | HIGH threshold headroom | A universal acceptable margin |
| LOW margin | NML = VIL,max − VOL,max > 0 | LOW threshold headroom | A universal acceptable margin |
| Input limit | Driver HIGH ≤ receiver VIN,max | Provided DC input limit is not exceeded | Power-sequence or transient safety |
| Loading | Driver current and edge-rate limits met | Selected fan-out is plausible | Signal integrity on the actual interconnect |
Voltage-Level Parameters
| Parameter | Definition | Belongs to | Condition to preserve |
|---|---|---|---|
| VOH,min | Guaranteed minimum HIGH output voltage | Driver | Use at the stated supply, load current, and temperature |
| VOL,max | Guaranteed maximum LOW output voltage | Driver | Use at the stated sink current and operating conditions |
| VIH,min | Minimum input voltage guaranteed as HIGH | Receiver | Inputs below this value are not necessarily HIGH |
| VIL,max | Maximum input voltage guaranteed as LOW | Receiver | Inputs above this value are not necessarily LOW |
| NMH | HIGH noise margin: VOH,min − VIH,min | Interface | Positive margin is necessary; zero is only a boundary |
| NML | LOW noise margin: VIL,max − VOL,max | Interface | Positive margin is necessary; include ground shift and noise |
| VIN,max | Maximum permitted input voltage | Receiver | A threshold pass does not prove absolute electrical safety |
| IIH / IIL | Input current at HIGH / LOW | Receiver | Contributes to fan-out and pull-up loading |
| IOH / IOL | Output source / sink capability | Driver | Guaranteed output voltage depends on this load |
| Cin | Input capacitance | Receiver | Affects edge rate, dynamic fan-out, and timing |
Input Regions
Guaranteed LOW
Undefined region
Guaranteed HIGH
The undefined region is not a permitted third logic state. Slow or noisy transitions through it can increase delay, chatter, current, or metastability risk depending on the input structure.
Logic Family Reference
| Family / convention | VOH,min | VOL,max | VIH,min | VIL,max | Use boundary |
|---|---|---|---|---|---|
| Classic 5 V TTL example | 2.4 V | 0.4 V | 2.0 V | 0.8 V | Historical reference values; verify the exact part |
| TTL-compatible CMOS input | Driver-specific | Driver-specific | Often TTL-like | Often TTL-like | Common in HCT-class devices, but part and supply conditions control |
| CMOS ratio example | Driver-specific | Driver-specific | Often near 0.7 VCC | Often near 0.3 VCC | A common convention for some families, never a universal guarantee |
| Low-voltage CMOS | Load- and VCC-specific | Load- and VCC-specific | Family-specific | Family-specific | Input tolerance and power sequencing can dominate mixed-voltage use |
These rows are orientation points, not replacement specifications. Family labels do not guarantee identical limits across manufacturers, variants, supply voltages, output loads, and temperature ranges.
Worked Interface Checks
Classic TTL reference
HIGH-level failure
LOW-level failure
Boundary is marginal
3.3 V example
Threshold pass, unsafe input
Loading, Fan-Out, and Dynamic Behavior
| Topic | Static check | Dynamic check |
|---|---|---|
| DC fan-out | Sum receiver input currents against IOH/IOL while preserving VOH/VOL | Also include leakage over temperature |
| Capacitive loading | Usually absent from static threshold arithmetic | Check rise/fall time, propagation delay, ringing, and driver stability |
| Open-drain | Check pull-up HIGH and sink-current LOW levels | Check RC rise time, wired loading, and bus timing |
| Ground offset | Subtract worst-case ground difference from available margins | Include return-path inductance and switching noise |
| Level translator | Check both directions, supplies, and enable state | Check direction control, bandwidth, edge rate, and power sequence |
Boolean State Versus Physical Voltage
Truth tables
Flip-flop tables
Logic compatibility
Guaranteed limits
Common Interpretation Mistakes
- Using VCC as guaranteed VOH,min.
- Using ground as guaranteed VOL,max.
- Comparing nominal supply labels instead of thresholds.
- Using typical values to claim guaranteed compatibility.
- Treating zero noise margin as robust.
- Ignoring the undefined input region.
- Assuming threshold compatibility proves input safety.
- Ignoring VIN,max and clamp-current limits.
- Ignoring output load current behind VOH/VOL limits.
- Counting fan-out without input current or capacitance.
- Assuming all CMOS inputs use 0.3/0.7 VCC thresholds.
- Assuming all TTL-compatible families share identical limits.
- Forgetting to check both directions of a bidirectional link.
- Ignoring power sequencing and unpowered-device behavior.
- Treating truth-table 0 and 1 as exact voltages.
Logic Interface Review Workflow
- 1Identify driver and receiver for each direction.
- 2Record actual supply rails and ground offsets.
- 3Extract guaranteed VOH,min and VOL,max at the intended load.
- 4Extract guaranteed VIH,min and VIL,max.
- 5Calculate NMH and NML.
- 6Check VIN,max, absolute maximums, and input tolerance.
- 7Check IOH/IOL against aggregate receiver loading.
- 8Check input capacitance and required edge timing.
- 9Review open-drain pull-ups where applicable.
- 10Review startup and power-down sequencing.
- 11Validate waveforms at the receiver pins.
- 12Repeat across voltage, load, and temperature corners.
Support reference
FAQ
What do VOH, VOL, VIH, and VIL mean?
VOH,min and VOL,max are guaranteed driver output limits. VIH,min and VIL,max are receiver input thresholds guaranteed as HIGH and LOW.
How do I check static logic-level compatibility?
Check VOH,min ≥ VIH,min and VOL,max ≤ VIL,max using guaranteed values under compatible supply, load, and temperature conditions.
What is HIGH noise margin?
HIGH noise margin is NMH = VOH,min − VIH,min. A positive result is threshold headroom for the HIGH state.
What is LOW noise margin?
LOW noise margin is NML = VIL,max − VOL,max. A positive result is threshold headroom for the LOW state.
What is the undefined input region?
A receiver input between VIL,max and VIH,min is not guaranteed to be interpreted as LOW or HIGH. It should not be treated as a third valid logic state.
Does a positive noise margin guarantee a safe connection?
No. Also check absolute maximum input voltage, input tolerance, clamp current, output current, fan-out, edge timing, power sequencing, and grounds.
Can a 3.3 V output drive a 5 V input?
Sometimes. Compare the driver's guaranteed VOH,min and VOL,max with the receiver's VIH,min and VIL,max, then check input limits and loading.
Can a 5 V output drive a 3.3 V input?
Only if the receiver is explicitly tolerant of that input voltage or an appropriate level translator or limiter is used. Threshold compatibility alone is insufficient.
Are CMOS thresholds always 0.3 VCC and 0.7 VCC?
No. Those ratios are common reference values for some CMOS inputs, but the exact device datasheet controls.
Are TTL voltage levels universal?
No. The familiar 5 V TTL thresholds are useful historical references, but family, device, supply, load, and temperature determine guaranteed limits.
What is fan-out?
Fan-out is the number of receiver inputs a driver can support while meeting output-voltage, current, capacitance, and timing requirements.
How are open-drain HIGH levels determined?
The pull-up supply, pull-up resistance, leakage, receiver loading, capacitance, and rise-time requirement establish the HIGH level and transition.
Why should I use guaranteed rather than typical values?
Typical values do not define worst-case compatibility. Use guaranteed minimum and maximum limits at the intended operating conditions.
Do truth tables specify real voltage levels?
No. Truth tables describe logical state relationships. A physical device maps those states to voltage, current, and timing limits in its datasheet.
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