Engineering Reference

UART, SPI and I²C Signals and Timing Reference

Quick-reference UART framing, SPI modes, I²C signals and pull-up timing, with formulas, terminology, engineering boundaries, and worked timing examples.

Reading Time: 14 min
Format: Signal and timing lookup
Updated: September 26, 2026

Interface Selection Snapshot

UART SPI and I2C comparison
Interface	Clocking	Typical signal set	Topology	Primary design check
UART	Asynchronous	TX, RX; optional flow control	Point-to-point logic link	Frame format and clock mismatch
SPI	Synchronous	SCLK, data in/out, one or more selects	Controller with selected peripheral(s)	Mode, clock limit, select timing, loading
I²C	Synchronous	SDA, SCL	Addressed multi-device bus	Pull-up range, capacitance, rise time, addressing

Signal Name Reference

Serial interface signal names
Signal	Role	Electrical behavior	Boundary to verify
UART TX	Transmit data	Push-pull logic	Idle level, polarity, framing, and voltage standard must match
UART RX	Receive data	Logic input	UART timing does not define RS-232 or RS-485 electrical levels
SPI SCLK	Serial clock	Controller-driven	CPOL defines idle level; CPHA defines the sampling edge
SPI COPI / MOSI	Controller-to-peripheral data	Usually push-pull	Naming and three-state behavior vary by device
SPI CIPO / MISO	Peripheral-to-controller data	Usually push-pull / three-state	Confirm inactive-device output behavior
SPI CS	Peripheral select	Usually active-low	Polarity and frame behavior are device-specific
I²C SDA	Bidirectional serial data	Open-drain / open-collector	Requires a pull-up and obeys wired-AND behavior
I²C SCL	Serial clock	Open-drain / open-collector	Rise time depends on pull-up resistance and bus capacitance

UART Framing and Timing

Frame length

Nframe = 1 start + Ndata + Nparity + Nstop. Thus 8N1 uses 10 line bits per payload byte.

Bit and frame time

tbit = 1 / baud and tframe = Nframe / baud.

Ideal payload rate

payload bytes/s = baud / Nframe. This excludes packet gaps and higher-layer overhead.

Baud error

error = (actual − target) / target × 100%. Acceptable error is implementation-dependent, not a universal percentage.

UART timing examples
Configuration	Frame bits	Bit time	Frame time	Ideal payload
9600 baud, 8N1	10	104.167 µs	1.04167 ms	960 bytes/s
115200 baud, 8N1	10	8.68056 µs	86.8056 µs	11,520 bytes/s
115200 baud, 8E1	11	8.68056 µs	95.4861 µs	10,472.7 bytes/s
1 Mbaud, 8N1	10	1 µs	10 µs	100,000 bytes/s

SPI Modes and Clock Timing

SPI CPOL and CPHA modes
Mode	CPOL	CPHA	Clock idle	Sample data	Shift data
0	0	0	Low	Leading edge	Trailing edge
1	0	1	Low	Trailing edge	Leading edge
2	1	0	High	Leading edge	Trailing edge
3	1	1	High	Trailing edge	Leading edge

Clock derivation

fSPI = fsource / divider. Verify the peripheral maximum and minimum clock timing.

Transfer time

tbit = 1/fSPI; an uninterrupted 8-bit transfer takes 8/fSPI.

Mode is necessary, not sufficient

Select setup/hold, inter-byte gaps, word length, bit order, dummy cycles, and peripheral response timing also matter.

Signal integrity

Faster edges make trace topology, return paths, loading, series damping, and probing more important even at modest clock frequencies.

SPI timing example
Source / divider	SPI clock	Bit time	8-clock byte	Ideal payload ceiling
48 MHz / 4	12 MHz	83.333 ns	666.667 ns	1.5 MB/s

I²C Pull-Up and Rise-Time Reference

I²C high levels are produced by pull-ups charging total bus capacitance. A resistor must be high enough to respect low-level sink-current capability and low enough to meet the applicable rise-time limit.

I2C pull-up formulas
Quantity	Formula	Interpretation
Minimum pull-up	Rmin = (VCC − VOL(max)) / IOL	Lower values demand more sink current
Maximum pull-up	Rmax = tr(max) / (0.8473 Cb)	Higher values produce slower RC edges
Estimated rise time	tr = 0.8473 Rp Cb	30% to 70% first-order RC convention
Bus RC constant	τ = Rp Cb	Useful physical time constant; not equal to the defined rise time

I2C worked pull-up example
Assumptions	Rmin	Rmax	Example 2.2 kΩ rise time
3.3 V; VOL 0.4 V; IOL 3 mA; tr 300 ns; Cb 100 pF	966.7 Ω	3.541 kΩ	186.4 ns

Rise-time limits, current capability, input thresholds, level shifters, leakage, bus buffers, and capacitance limits must come from the applicable current specification and device datasheets.

Protocol and Electrical Boundaries

UART is not RS-232

UART describes framing and logic timing. RS-232, RS-485, CMOS UART, and other physical layers use different voltages and electrical behavior.

SPI is not one electrical standard

SPI is a widely used interface convention with device-specific timing. Confirm mode, levels, clock limit, select behavior, and data direction in both datasheets.

I²C is shared and open-drain

Addressing, arbitration, clock stretching, repeated starts, pull-ups, and level translation affect system behavior. Device support varies.

No universal cable limit

None of these names alone supplies a universal distance limit. Use an appropriate transceiver and validate timing, thresholds, noise margin, return paths, and EMC.

Common Design Mistakes

Treating UART baud rate as the only compatibility setting.
Forgetting start, parity, or stop-bit overhead in throughput.
Connecting RS-232 voltage levels directly to CMOS UART pins.
Selecting the wrong SPI CPOL/CPHA mode.
Assuming SPI clock frequency equals useful payload throughput.
Leaving inactive SPI peripheral outputs driving the bus.
Using push-pull outputs on an I²C bus.
Choosing an I²C pull-up without bus capacitance.
Checking I²C rise time but not sink current or VOL.
Assuming a speed label overrides device-specific timing.
Ignoring logic-level compatibility across supply domains.
Quoting a universal maximum distance.
Treating controller/peripheral signal names as always consistent.
Using formatted display values for timing-chain calculations.

Serial Interface Review Workflow

1Identify the interface and exact physical voltage domain.
2Trace signal direction from both device datasheets.
3Confirm frame format, SPI mode, or I²C addressing behavior.
4Calculate bit, frame, and useful payload timing.
5Include protocol and transaction overhead.
6Check clock accuracy and timing margins.
7For I²C, estimate total bus capacitance.
8Calculate both minimum and maximum pull-up resistance.
9Verify thresholds, sink current, and rise time.
10Review topology, return paths, loading, and edge rate.
11Validate with oscilloscope measurements at the receiver.
12Use the current normative specification for compliance limits.

Support reference

FAQ

What is the difference between baud rate and bit rate in UART?

For ordinary binary UART signaling, one symbol carries one bit, so baud rate and line bit rate are numerically equal. Baud and bit rate are not universal synonyms for every modulation system.

How many bits are in an 8N1 UART frame?

An 8N1 frame has one start bit, eight data bits, no parity bit, and one stop bit, for 10 transmitted bits per data byte.

How do I calculate UART frame time?

Divide total frame bits by baud rate. At 115200 baud, an 8N1 frame takes about 86.81 microseconds.

Why can two UART devices fail at the same nominal baud rate?

Clock error, polarity, data bits, parity, stop bits, logic thresholds, voltage standards, sampling behavior, and wiring must also be compatible.

What do CPOL and CPHA mean in SPI?

CPOL selects the clock idle level. CPHA selects whether data is sampled on the leading or trailing clock edge. Both endpoints must use the same mode.

Are MOSI and MISO the only valid SPI signal names?

No. COPI and CIPO are also used, and component datasheets may use SDI, SDO, DIN, DOUT, or device-specific names. Follow the actual signal direction.

Does SPI clock rate equal payload throughput?

Only as an ideal upper bound. Command, address, dummy, select, turnaround, and idle cycles reduce useful payload throughput.

Why does I²C need pull-up resistors?

SDA and SCL are normally open-drain or open-collector signals. Devices pull the bus low, while pull-up resistors return it high.

How is the I²C minimum pull-up resistance estimated?

Use Rmin = (VCC − VOL(max)) / IOL. A lower resistance demands more low-level sink current.

How is the I²C maximum pull-up resistance estimated?

For the common 30% to 70% RC rise-time convention, Rmax = tr(max) / (0.8473 Cb). Use the applicable specification and measured bus capacitance.

Is one I²C pull-up value correct for every board?

No. Supply voltage, device sink capability, bus capacitance, speed mode, leakage, level shifting, and topology all affect the valid range.

Can UART, SPI, and I²C voltage levels be assumed compatible?

No. Protocol timing does not guarantee compatible logic thresholds, supply domains, inversion, or transceiver standards. Check every device datasheet.

What limits serial interface distance?

Driver strength, thresholds, edge rate, impedance, capacitance, grounding, noise, topology, cable construction, and transceiver type matter. These logic-bus names alone do not define a universal maximum distance.

Which document controls when this table differs from a device datasheet?

Use the current applicable interface specification and the exact device datasheets. This page is a design lookup, not a replacement for normative limits.

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