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Engineering Guide

Resistor Networks, Voltage Divider Loading, and SMD Markings

Real resistor networks are shaped by topology, load impedance, tolerance, power, working voltage, temperature, and parasitics. A correct nominal value or marking decode is necessary, but not sufficient.

ResistorsIntermediate18 min readUpdated October 7, 2026

Network Design Workflow

StepActionEngineering Check
Decode and verifyInterpret the marking system, package, tolerance, and datasheet before using the nominal value.
Reduce the networkIdentify true series and parallel branches; do not combine parts that share neither the same current nor both nodes.
Find source equivalentUse Thevenin voltage and resistance to expose loading, bias current, and ADC acquisition effects.
Apply the loadReplace the lower divider leg by its parallel combination with the real load.
Check toleranceEvaluate useful worst-case corners or statistical behavior rather than only nominal ratios.
Check powerCalculate each resistor's current, dissipation, pulse energy, voltage stress, and temperature rise.
Check dynamic behaviorInclude node capacitance, input sampling, noise, and parasitic capacitance where bandwidth matters.
ValidateMeasure resistance out of circuit when possible and verify loaded voltage, current, power, and temperature.

Series, Parallel, and Loaded Dividers

Formula reference

Network equations

Series: Req = sum(Ri)Parallel: 1/Req = sum(1/Ri)Unloaded divider: Vout = Vin Rlow/(Rhigh + Rlow)Loaded lower leg: Rlower,eff = Rlow parallel RloadVth = Vin Rlow/(Rhigh + Rlow)Rth = Rhigh parallel Rlow

Variable definitions

Series parts must carry the same current
Parallel parts must share both nodes
Thevenin form exposes loading
Recalculate tolerance and power corners

Use the Series & Parallel Resistor Calculator and Voltage Divider Calculator for nominal networks, then apply the real load and error budget.

Power and SMD Markings

Formula reference

Stress and marking checks

P = I squared R = V squared/RThree-digit code: AB x 10^C ohmsFour-digit code: ABC x 10^D ohmsR marks a decimal point

Variable definitions

Check individual resistor power
Verify package working voltage and pulse energy
EIA-96 uses a separate code table
Unmarked parts require BOM or measurement evidence

Use the SMD Resistor Code Calculator for supported marking systems. The existing color-code Guide remains the authority for leaded band markings.

Worked Examples

Series network

1 kohm + 2.2 kohm + 4.7 kohm gives 7.9 kohms; the same current flows through each part.

Parallel pair

10 kohms in parallel with 10 kohms gives 5 kohms; each equal branch shares half the ideal current.

Unloaded divider

10 V through 10 kohms over 10 kohms produces 5 V with no load.

Loaded divider

Adding a 10 kohm load across the lower 10 kohm resistor makes the lower equivalent 5 kohms and output 3.33 V.

Thevenin form

The unloaded 10k/10k divider has Vth = 5 V and Rth = 5 kohms.

Power

A 10 kohm resistor across 10 V dissipates 10 mW.

Tolerance corner

For a divider, maximum output uses the high-side resistor at minimum and low-side resistor at maximum.

Three-digit SMD

472 means 47 x 10^2 ohms, or 4.7 kohms.

Four-digit SMD

1001 means 100 x 10^1 ohms, or 1 kohm.

Decimal marking

4R7 means 4.7 ohms; R acts as the decimal point.

Common Mistakes

Combining resistors as series merely because they are drawn in a row.
Combining branches as parallel when they do not share both nodes.
Using the unloaded divider equation with a finite load.
Ignoring ADC input sampling and acquisition time.
Ignoring source and input bias currents.
Applying the same tolerance direction to both divider resistors for a worst-case ratio.
Checking total network power but not individual resistor power.
Ignoring resistor working-voltage and pulse ratings.
Reading 472 as 472 ohms instead of 4.7 kohms.
Treating every four-character code as the same marking system.
Assuming an unmarked tiny SMD resistor can be identified visually.
Measuring a resistor in circuit without accounting for parallel paths.

Related Calculators

Support reference

FAQ

How do resistors add in series?

Series resistances add directly when the same current must flow through each resistor and their shared nodes have no other branches.

How do resistors add in parallel?

Parallel conductances add. For two resistors, equivalent resistance is their product divided by their sum.

How do I calculate a voltage divider?

For an unloaded divider, multiply input voltage by the lower resistance divided by the sum of upper and lower resistances.

How does a load change a voltage divider?

The load is in parallel with the lower resistor, reducing the effective lower resistance and usually lowering output voltage.

What is the Thevenin resistance of a divider?

With the ideal source set to zero, the upper and lower divider resistors appear in parallel at the output node.

How should divider tolerance be checked?

Evaluate resistor tolerance corners that maximize and minimize the ratio, then add reference, source, load, bias-current, and temperature errors as applicable.

How do I calculate resistor power?

Use I squared R, V squared divided by R, or VI for each resistor under the relevant steady and transient condition.

What does a three-digit SMD resistor code mean?

The first two digits are significant figures and the third is a base-10 multiplier, with special low-value and EIA-96 systems handled separately.

What does 4R7 mean on a resistor?

R is the decimal marker, so 4R7 represents 4.7 ohms.

What does 000 mean on an SMD resistor?

It commonly identifies a zero-ohm link, but package markings and manufacturer documentation should be verified.

Why can my measured resistor value be wrong in circuit?

Other connected components create parallel or active paths. Isolate one terminal when safe and discharge the circuit before measurement.

How should I validate a resistor network?

Verify markings and BOM, calculate loaded tolerance and power corners, and measure resistance, node voltage, current, and temperature in the actual circuit.

Summary

Confirm the marking and topology, reduce the ideal network, expose loading with a Thevenin equivalent, and close the design with tolerance, power, voltage, pulse, temperature, noise, and dynamic-input checks.