Practical Op-Amp Integrators and Differentiators: Leakage, Reset, and Noise

Choose the Signal Operation

An integrator converts a constant input into a ramp and averages a varying input in time. A differentiator responds to rate of change, including unwanted fast edges. Define input amplitude, duration, frequency band, output swing, acceptable drift, and reset or settling behavior before selecting R and C. The Op-Amp Integrator & Differentiator Calculator evaluates the ideal RC relationship; it deliberately does not model practical limit components.

Bound the Integrator at DC

Put a resistor Rf in parallel with the feedback capacitor to provide a DC return path. For the simple inverting circuit with input resistor Rin, the idealized transfer is H(s) = -(Rf/Rin)/(1+sRfC). At frequencies well above 1/(2πRfC), this approaches -1/(sRinC); at DC, gain is finite at -Rf/Rin. Choose the transition comfortably below the lowest frequency that must be integrated, then verify that offset and input bias current still fit inside the output headroom. Large Rf raises sensitivity to bias, leakage, contamination, and board humidity.

For Rin = 10 kΩ, C = 100 nF, and Rf = 1 MΩ, fL is about 1.59 Hz and the DC gain magnitude is 100. An ideal 1 V constant input would initially ramp at -1 V/ms, but the leaky circuit approaches its finite DC equilibrium instead of ramping forever. Do not use that 100 V ideal equilibrium as a physically attainable output: the amplifier clips at its available output swing.

Set an Initial State and Reset Strategy

A switched integrator must define what voltage remains on C at the start of each measurement. A reset switch across C can discharge it, but switch on-resistance, charge injection, leakage, feedthrough, and recovery time matter. A finite Rf alone provides exponential recovery with time constant RfC; after one time constant about 37% of an initial offset remains in the ideal linear model. Reset only when its disturbance can be tolerated, and allow settling before sampling.

A 10 ms integration window with Vin = 0.2 V and RinC = 10 ms predicts a -0.2 V ideal change. That is useful only when the output starts from a known voltage and remains within the actual output swing. The op-amp input common-mode range, supply, load, and output current can invalidate an otherwise correct ramp calculation.

Limit the Differentiator Bandwidth

The ideal differentiator raises signal and noise gain with frequency. A common bounded version adds a resistor Ri in series with the input capacitor C1 and a capacitor Cf parallel to feedback resistor Rf. For this explicitly labeled inverting topology, Zin = Ri + 1/(sC1), Zf = Rf/(1+sRfCf), and H(s) = -Zf/Zin. At low frequency it approaches -sRfC1; above the input corner, Ri limits the drive, and the feedback capacitor rolls off the high-frequency transfer. This is not a universal differentiator formula for differently labeled schematics.

For Rf = 10 kΩ and C1 = 10 nF, the low-frequency differentiation coefficient is 100 µs. A 1 V/ms ramp would predict -0.1 V while the approximation holds. A 1 V step has an unbounded ideal derivative, so it is inappropriate to report one finite ideal step-output voltage; bandwidth and physical edge time determine the real transient.

Check Op-Amp and Component Limits

The Slew Rate Calculator checks sine-wave full-power limits; the Gain Bandwidth Product Calculator provides a first-pass bandwidth estimate. Neither substitutes for loop-gain analysis of a capacitive feedback network. Review the Active Filter and Op-Amp Dynamic Limits Guide for device-wide constraints.

Bench Verification

Apply a calibrated constant or square-wave input to check integration slope, initial state, clipping, and reset recovery. Sweep a small sine signal to find the transition between finite low-frequency gain and integration. For differentiation, use a finite-slew ramp and controlled-bandwidth edges, then inspect noise, overshoot, phase, and peak output. Repeat at the intended supply, temperature, source impedance, load, and board layout. Never infer stability from one clean nominal waveform.

Common Mistakes

• Treating an ideal integrator as stable at DC.
• Sizing only RC without specifying initial capacitor voltage.
• Expecting a leakage resistor to make every DC error disappear.
• Ignoring reset-switch charge injection and recovery.
• Using an ideal step derivative as a finite output prediction.
• Applying a practical topology equation to differently labeled components.
• Ignoring the differentiator's high-frequency noise gain.
• Calling 1/(2πRC) the complete practical bandwidth.
• Checking GBW but not phase margin or output swing.
• Assuming rounded ideal-calculator output is measured circuit behavior.