Engineering Guide
MOSFET SOA and Thermal Design: Loss, Transient Impedance, Avalanche, and Derating
A MOSFET thermal result is trustworthy only when the electrical loss waveform, hot device parameters, package and board heat path, transient behavior, and SOA limits describe the same operating condition.
Electrothermal Design Workflow
| Step | Action | Engineering Check |
|---|---|---|
| Define every operating state | Include normal conduction, transitions, dead time, startup, current limit, short circuit, hot swap, reverse current, and shutdown. | |
| Build the loss budget | Add conduction, switching overlap, output-capacitance, gate-drive, body-diode, reverse-recovery, avalanche, and linear-mode loss where applicable. | |
| Use hot parameters | Iterate RDS(on), switching behavior, leakage, and diode characteristics at the estimated junction temperature. | |
| Model the thermal path | Choose junction-to-case, case-to-sink, junction-to-board, or junction-to-ambient paths that match the package and assembly. | |
| Check transient temperature | Use transient thermal impedance for pulses and superpose repeated events only within the model's assumptions. | |
| Check SOA | Plot voltage-current-time points against the applicable DC or pulse SOA curve at the real starting temperature. | |
| Check avalanche and clamps | Treat avalanche energy and repetitive stress as bounded ratings, not a universal substitute for a clamp. | |
| Validate hardware | Measure VDS, ID, switching energy, case/board temperature, cooling conditions, and protection response over corners. |
Complete MOSFET Loss Budget
| Loss | First-Order Model | Boundary |
|---|---|---|
| Conduction | Irms²RDS(on) | Use RDS(on) at actual VGS and hot TJ |
| Switching overlap | fsw∫vDS(t)iD(t)dt | Measure or model each edge; linear-ramp estimates are only first order |
| Output capacitance | Energy from Eoss/Qoss data | Coss is nonlinear; 0.5CV² may be inaccurate |
| Gate drive | QgVdrivefsw | Usually dissipated mainly in driver and gate resistance |
| Body diode | VFIFt plus recovery effects | Depends on dead time, temperature, and commutation |
| Reverse recovery | Commutation overlap energy | Includes partner-switch and loop-inductance stress |
| Avalanche | ∫vDSiDdt during unclamped event | Check EAS, current, temperature, and repetitive limits |
| Linear mode | VDSID over dwell time | Must satisfy SOA and thermal stability, not only power |
Use the MOSFET Total Power Dissipation Calculator to combine supported terms, then reconcile its assumptions with the actual topology and measured waveforms.
Steady and Transient Junction Temperature
Formula reference
Thermal relationships
TJ = Tref + PlossRθΔTJ,pulse = PpulseZθ(t)Rθ,total = RθJC + RθCS + RθSAVariable definitions
- Use only a continuous thermal path with compatible reference points
- RθJA already includes an assumed environment
- Transient Zθ is waveform and duty dependent
- Iterate loss with hot parameters
The Junction Temperature Calculator and Thermal Resistance Calculator support first-pass steady paths. They do not replace transient impedance curves or a board-specific thermal model.
SOA, Linear Mode, and Avalanche
Use the MOSFET SOA Calculator to organize voltage, current, time, and power checks, then compare against the manufacturer's applicable graph. Linear mode can suffer localized heating even below a simple constant-power line. Avalanche checks require current, energy, starting temperature, repetition, and the exact qualification conditions.
Worked Examples
Hot conduction
A 20 A RMS current through 8 mΩ hot RDS(on) produces 3.2 W conduction loss.
Switching loss
If measured turn-on plus turn-off energy is 150 µJ at 50 kHz, switching loss is 7.5 W.
Total loss
Combining 3.2 W conduction, 7.5 W switching, and 0.8 W diode/recovery loss gives 11.5 W before thermal iteration.
Steady junction estimate
At 11.5 W and an applicable 4 °C/W junction-to-coolant path from 60 °C, TJ estimates to 106 °C.
Pulse temperature
A 100 W, 10 ms pulse with ZθJC(10 ms) = 0.2 °C/W raises junction about 20 °C above the starting case temperature.
Linear startup
A hot-swap MOSFET carrying 5 A while dropping 20 V sees 100 W; pulsed SOA at the startup duration governs acceptability.
Parallel sharing
Positive hot RDS(on) temperature coefficient can aid steady sharing, but gate-loop, source inductance, threshold, and transient differences still matter.
Avalanche
A 2 mJ inductive event below a headline EAS rating still requires checks for current, starting TJ, clamp voltage, repetition, and qualification conditions.
PCB path
A package RθJA value from a datasheet test board cannot be transferred directly to a smaller copper area or enclosed product.
Measurement
Double-pulse testing provides edge energy and overshoot; thermal validation establishes whether the repeated operating cycle reaches an acceptable TJ.
Common Mistakes
Related Calculators
Support reference
FAQ
What is MOSFET safe operating area?
SOA is the allowed combination of drain voltage, drain current, pulse duration, duty conditions, and temperature stated by the manufacturer.
How is MOSFET junction temperature estimated?
Add dissipated power times the applicable steady thermal resistance to its reference temperature, or use transient thermal impedance for time-limited pulses.
Why must RDS(on) be evaluated hot?
RDS(on) generally rises with junction temperature, increasing conduction loss and changing the self-consistent thermal result.
What losses belong in a MOSFET budget?
Include conduction, switching overlap, output-capacitance, gate-drive, body-diode, reverse-recovery, avalanche, and linear-mode losses that occur in the topology.
Is RθJA a property of the MOSFET alone?
No. It depends strongly on the package test board, copper, vias, airflow, orientation, enclosure, and neighboring heat sources.
When should transient thermal impedance be used?
Use it for pulses shorter than thermal steady state, following the datasheet's pulse-shape, duty-cycle, and reference-temperature assumptions.
Can any switching MOSFET operate in linear mode?
Not safely by assumption. Linear-mode stability and DC/pulsed SOA vary widely, and some switching-optimized devices have limited linear capability.
What is MOSFET avalanche energy?
It is energy absorbed while the MOSFET clamps an inductive voltage through avalanche under specified test conditions. It is not an unlimited repetitive rating.
Does paralleling MOSFETs divide current equally?
Not automatically. RDS(on), threshold, gate impedance, source inductance, layout, cooling, and dynamic timing all affect sharing.
How is MOSFET switching loss measured?
Integrate simultaneous VDS and ID during each transition with suitable probes, deskew, bandwidth, and a representative switching loop.
How much thermal margin should I leave?
There is no universal value. Account for parameter spread, cooling degradation, ambient extremes, transients, model uncertainty, lifetime, and protection response.
How should a MOSFET thermal design be validated?
Correlate electrical loss measurements, package or board temperatures, calibrated thermal models, cooling conditions, and protection tests over real operating corners.
Summary
Build a topology-complete loss budget, iterate hot parameters, model the actual steady and transient heat path, verify every operating point against SOA and avalanche limits, derate for uncertainty, and correlate the model with electrical and thermal measurements.