Engineering Guide
UART and CAN Timing: Clock Error, Sampling, Bit Segments, and Propagation
A nominal baud or bit rate is only the first line of a timing budget. Reliable UART reception depends on relative clock error and where each bit is sampled. Reliable CAN communication adds integer time quanta, phase segments, resynchronization, and physical propagation delay. This guide develops those two timing models without treating either calculator as a protocol simulator.
A Timing-Budget Workflow
UART and CAN are electrically and logically different, but both require a clock-derived nominal bit time plus margin for real hardware. Use the UART Timing Calculator for asynchronous frames and the CAN Bus Bit Timing Calculator for quantized CAN segments.
| Step | Check | Engineering action |
|---|---|---|
| 1 | Define the clock | Use the controller clock that actually feeds the UART or CAN timing block, including prescalers. |
| 2 | Choose nominal rate | State baud or bit rate and distinguish it from payload throughput. |
| 3 | Resolve timing | For UART, resolve frame and sample timing. For CAN, solve BRP and integer bit segments. |
| 4 | Budget mismatch | Include oscillator tolerance, temperature drift, divider quantization, and endpoint mismatch. |
| 5 | Budget propagation | Include cable, transceiver, isolation, connector, and node delays where applicable. |
| 6 | Verify hardware | Check controller register rules, datasheets, oscilloscope traces, and worst-case temperature. |
UART Asynchronous Timing Model
UART has no continuously shared clock. The receiver detects a start edge, then uses its own clock to predict sampling instants. A framing calculation therefore needs more than a nominal baud value: it needs the complete frame format and a clock-error budget for both endpoints.
For a conventional frame, parity contributes either zero or one bit. Stop configurations may include one, one-and-a-half, or two bit periods where supported. A packet-time result assumes frames are contiguous; firmware, DMA, flow control, turnaround, and idle gaps must be added separately.
| Quantity | Equation | Meaning |
|---|---|---|
| Bit time | tbit = 1 / BaudRate | Nominal duration of one UART symbol when binary NRZ carries one bit per symbol. |
| Frame bits | Nframe = Nstart + Ndata + Nparity + Nstop | Every transmitted framing bit consumes time. |
| Frame time | tframe = Nframe / BaudRate | Time from the start bit through the configured stop bits. |
| Packet time | tpacket = Nbytes x Nframe / BaudRate | Continuous-frame estimate before software gaps or flow control. |
| Baud error | e = (Bactual - Bexpected) / Bexpected x 100% | Signed local error relative to the intended rate. |
| Sample instant | tsample = tbit x SamplePosition | Nominal sampling location inside a received bit. |
Formula reference
UART timing equations
t_bit = 1 / BaudRateN_frame = N_start + N_data + N_parity + N_stopt_frame = N_frame / BaudRatet_packet = N_bytes x N_frame / BaudRateBaudError(%) = (B_actual - B_expected) / B_expected x 100Variable definitions
- Use unrounded internal values for chained calculations
- Baud equals bit rate numerically only for one-bit-per-symbol signaling
- Packet time excludes unmodeled inter-frame delays
Clock Error, Sampling, and Accumulated Drift
If the transmitter runs fast while the receiver runs slow, their relative error is worse than either local error alone. After synchronization at the start edge, the predicted receiver sample drifts relative to transmitted bit boundaries as the frame progresses. Receiver oversampling, edge qualification, resynchronization behavior, jitter, and sample position determine the usable margin.
A single “maximum UART error” percentage is therefore unsafe as a universal rule. Build a worst-case endpoint budget from oscillator tolerance, temperature, aging, and divider error, then verify the UART datasheets and the longest supported frame.
CAN Time Quanta and Bit Segments
CAN constructs each nominal bit from an integer number of time quanta. The synchronization segment is one quantum. TSEG1 covers the propagation and first phase portions in the conceptual model; TSEG2 covers the second phase portion. The sample point lies between TSEG1 and TSEG2.
Multiple settings can produce the same bit rate. Prefer a candidate that also meets the controller's BRP, segment, and SJW ranges; provides a suitable sample point; and leaves enough propagation and oscillator margin for the network.
| Quantity | Equation | Meaning |
|---|---|---|
| Time quantum | tq = BRP / fCAN | Smallest nominal timing unit in the adopted generic model. |
| Quanta per bit | NTQ = 1 + TSEG1 + TSEG2 | The synchronization segment is one time quantum. |
| Bit time | tbit = tq x NTQ | Nominal duration of one CAN bit. |
| Bit rate | BitRate = fCAN / (BRP x NTQ) | Nominal arbitration-phase rate for the chosen divider and segments. |
| Sample point | SP = (1 + TSEG1) / NTQ x 100% | Location at the end of TSEG1. |
| Segment identity | TSEG1 = PropSeg + PhaseSeg1 | Useful conceptual decomposition where the controller exposes it. |
Formula reference
Generic nominal CAN timing
t_q = BRP / f_CANN_TQ = 1 + TSEG1 + TSEG2BitRate = f_CAN / (BRP x N_TQ)SamplePoint(%) = (1 + TSEG1) / N_TQ x 100BitRateError(%) = (Actual - Target) / Target x 100Variable definitions
- The equations use physical values, not device-specific register encodings
- Many controllers store BRP and segment values as value minus one
- CAN FD data-phase timing is outside this guide
SJW, Resynchronization, and Propagation Delay
CAN receivers use observed edges to resynchronize. The synchronization jump width limits the permitted correction, and it must not exceed the applicable controller segment limit. More SJW is not automatically better: phase segments, controller rules, oscillator tolerance, and network behavior must remain coherent.
Propagation is a round-trip system concern, not merely cable length divided by velocity. Include transmitter and receiver delays, cable delay, connectors, isolation, stubs, and node circuitry. PropSeg is intended to accommodate physical delay, while phase segments support sampling and resynchronization margin.
Worked Examples
UART 115200 Baud, 8N1
- Nframe = 1 start + 8 data + 0 parity + 1 stop = 10 bits.
- tbit = 1 / 115200 = 8.68056 us.
- tframe = 10 / 115200 = 86.8056 us.
- A 32-byte continuous packet takes 32 x 10 / 115200 = 2.77778 ms before inter-frame gaps.
UART Divider Error
- Expected baud = 115200; actual baud = 115384.615.
- Baud error = (115384.615 - 115200) / 115200 x 100% = +0.1603%.
- This local error is not the complete link mismatch; repeat the calculation for the remote endpoint and combine worst-case clock directions.
UART Sampling Margin
- At 9600 baud, tbit = 104.167 us.
- A 50% nominal sample position occurs 52.083 us after the bit boundary.
- Clock mismatch accumulates from the start-edge synchronization through later data bits, so the last sampled bit usually has less timing margin than the first.
CAN 500 kbit/s from 16 MHz
- Choose BRP = 2 and NTQ = 16.
- tq = 2 / 16 MHz = 125 ns.
- Bit rate = 16 MHz / (2 x 16) = 500 kbit/s, and tbit = 2 us.
- With TSEG1 = 13 and TSEG2 = 2, sample point = (1 + 13) / 16 = 87.5%.
CAN Propagation Budget
- A 40 m cable at 5 ns/m contributes about 200 ns one way.
- Add transmitter, receiver, connector, isolation, and node delays before judging whether the propagation segment is sufficient.
- Do not convert this example into a universal maximum cable length; topology, cable, transceivers, bit timing, and standards constraints all matter.
Practical Validation
Common Mistakes
- Using payload bytes divided by baud rate and omitting UART framing bits.
- Considering only one UART endpoint's oscillator error.
- Quoting a universal UART mismatch limit without receiver context.
- Rounding baud or bit time before later calculations.
- Using the CPU clock instead of the peripheral timing clock.
- Confusing physical CAN segment values with encoded register fields.
- Selecting a CAN candidate by rate error alone while ignoring sample point and SJW.
- Treating 87.5% as a universal CAN sample point.
- Estimating CAN length from cable delay while omitting transceiver and node delays.
- Applying nominal CAN timing equations directly to a CAN FD data phase.
Related Calculators
Related Engineering Guides
Frequently Asked Questions
Support reference
FAQ
Is UART baud rate the same as bit rate?
For ordinary binary NRZ UART, one symbol represents one bit, so the numerical values normally match. Baud and bit rate are still different concepts and are not interchangeable for every modulation scheme.
How is UART frame time calculated?
Add the start, data, parity, and stop bits, then divide the total by baud rate. Include software gaps separately when they are present.
What causes UART baud mismatch?
Clock tolerance, temperature drift, oscillator aging, integer or fractional divider quantization, and use of an incorrect peripheral clock can all contribute.
What is the maximum acceptable UART baud error?
There is no universal percentage. It depends on both endpoints, receiver oversampling and resynchronization, frame length, sample position, jitter, and hardware implementation.
What is a CAN time quantum?
A time quantum is the clock-derived unit used to construct the CAN bit time. In this guide's generic model, tq equals BRP divided by the CAN timing clock.
How is the CAN sample point calculated?
For NTQ = 1 + TSEG1 + TSEG2, the nominal sample point is (1 + TSEG1) / NTQ times 100 percent.
What does SJW do in CAN timing?
The synchronization jump width limits how much a bit may be lengthened or shortened during resynchronization. It must obey the controller's segment and register constraints.
Why does CAN propagation delay matter?
A transmitter must observe the bus response within the timing assumptions used for arbitration and synchronization. Cable, transceiver, isolation, and node delays consume that budget.
Does an 87.5 percent CAN sample point always work?
No. It is common in some designs but not universal. Required timing depends on rate, network length, propagation delay, oscillator tolerance, transceivers, and controller rules.
Can this guide calculate CAN FD data-phase timing?
No. The equations here describe a generic nominal CAN bit-time model. CAN FD data-phase timing and transceiver-delay compensation require controller-specific analysis.
Why can two valid CAN timing settings behave differently?
They may have the same bit rate but different numbers of time quanta, sample points, phase segments, SJW, and oscillator or propagation margins.
Should calculated settings be copied directly into registers?
Not without checking the controller manual. Many devices encode BRP and segment fields as value minus one and impose device-specific ranges and dependencies.
Summary
UART timing closes when frame length, both endpoint clocks, sample behavior, and accumulated drift remain compatible. CAN timing closes when the clock divider, integer segments, sample point, SJW, propagation delay, oscillator tolerance, and controller constraints agree. Calculate with full precision, preserve each model's boundaries, and verify the final register settings and waveforms on real hardware.