SPI Timing Budget: Clock, Data, Chip Select, and Board-Level Verification

Start with the Actual Devices

Record controller peripheral clock and divider choices, peripheral SCLK maximum, input setup and hold requirements, output clock-to-data delay, CS setup and hold times, supply range, temperature range, and whether MISO releases when deselected. The SPI Clock Calculator converts a divider to fSCLK, bit time, and ideal block transfer time. It does not calculate setup, hold, PCB propagation, or analog edge quality.

Map the Launch and Sample Edges

CPOL sets the idle clock level; CPHA selects which edge shifts and which samples. Confirm the controller and peripheral use the same interpretation. For a common Mode 0 transfer, data is captured on a rising edge and changes on a falling edge. Another mode can move the first-bit requirement or the available interval. Draw one timing diagram for MOSI and another for MISO using the chosen devices, not a generic SPI label.

A controller can meet its own pin timing yet fail at a distant peripheral after clock/data skew. Conversely, the return path adds an outbound clock flight and an inbound MISO flight. Do not combine minimum and maximum numbers from different voltage or temperature conditions without a documented corner assumption. See the Serial Interface Guide for high-level protocol comparisons; this page owns physical SPI timing closure.

Budget the MISO Return Path

For a specific opposite-edge launch/sample arrangement, an illustrative MISO setup budget is half the SCLK period minus outbound clock flight, peripheral clock-to-output maximum, return data flight, controller input setup, and an explicit uncertainty allowance. Verify the actual edge relationship and device timing definitions first; some controllers provide a delayed sample or a different phase relationship.

At 20 MHz, T/2 = 25 ns. If outbound clock flight is 3 ns, peripheral tCO,max is 8 ns, return flight is 3 ns, controller setup is 4 ns, and uncertainty is 2 ns, the remaining illustrative setup margin is 5 ns. A longer route or a different sampling convention can consume it. Check hold with minimum clock-to-output and minimum flight times separately; the setup inequality cannot certify hold.

Include MOSI, CS, and Gaps

For MOSI, compare controller data launch with clock arrival at the peripheral and its input setup/hold specifications. Depending on route lengths, clock can arrive early or late relative to data. CS may need to assert before the first SCLK edge, remain active past the last edge, and stay inactive for a specified recovery interval before another command. Continuous SCLK time excludes command/address bytes, dummy clocks, CS gaps, firmware scheduling, DMA start latency, and device processing delay.

For a 4-byte command/address phase plus 256 payload bytes at 20 MHz, uninterrupted shifting of 260 bytes takes 104 µs. If setup, hold, interburst, and firmware delays total 16 µs, the transaction is about 120 µs and useful 256-byte payload rate is about 17.1 Mbit/s, not 20 Mbit/s. Actual protocol direction and dummy cycles may reduce it further.

Check the Shared-Bus and Board Boundary

On a multi-peripheral bus, verify each device releases MISO when deselected and that no two CS lines overlap during configuration changes. Devices can require different CPOL/CPHA modes, SCLK ceilings, supply levels, or CS recovery intervals. Do not assume a level shifter preserves timing or edge shape; include its propagation delay and output-drive behavior. Route clock with a continuous return path, control stubs and ringing, and measure at the receiving pins. Series damping, if needed, is a board-specific signal-integrity decision, not a universal resistor value.

Verification Matrix

Use a probe with suitable bandwidth and a short return path. Capture worst-case devices, longest routes, highest clock setting, and low/high supply plus temperature corners. A logic analyzer shows decoded traffic but may hide analog threshold or ringing failures; pair it with an oscilloscope when timing margin is small.

Common Mistakes

• Equating divider-derived SCLK with guaranteed link speed.
• Using the wrong CPOL/CPHA mode or first-bit convention.
• Budgeting MISO without outbound clock and return data delay.
• Checking setup but not hold.
• Using typical tCO instead of a valid maximum corner.
• Ignoring CS setup, hold, and deselected recovery.
• Counting payload bytes but not command and dummy clocks.
• Assuming SCLK/8 is sustained useful throughput.
• Ignoring level-shifter delay or MISO bus contention.
• Measuring only at the controller pin rather than the receiver.
• Treating a clean decoded capture as proof of analog margin.
• Applying the illustrative half-cycle equation to every SPI mode.

Primary Engineering Sources

Consult Microchip SPI timing guidance for mode conventions and Microchip CS hold guidance for the importance of select timing. Verify numeric limits against the exact controller and peripheral datasheets.