I²C Bus Design: Pull-Up Window, Capacitance, Clock Stretching, and Validation

Inventory the Installed Bus

List the controller, all targets, SDA and SCL traces, connectors, cable, translators, buffers, test points, and pull-up resistors already mounted on every module. Record each part's voltage, input capacitance, leakage, guaranteed low-level sink current at VOL, rise/fall timing, and clock-stretch support. Verify every participant supports the chosen bus mode. The Serial Interface Guide introduces the RC constraint; this guide treats the distributed bus as a design and validation problem.

Solve a Resistance Window, Not One Magic Value

In a simple passive-RC model, the weakest permitted low-state driver sets a lower bound on resistance; the allowed 30%-to-70% rise time and total bus capacitance set an upper bound. Use the I²C Pull-Up Resistor Calculator for this first-pass interval, then compare the selected physical resistor with actual devices and scope measurements. Apply the check independently to SDA and SCL if their capacitance differs.

For Vpullup = 3.3 V, VOL,max = 0.4 V, IOL,max = 3 mA, Cbus = 200 pF, and a 300 ns rise-time limit, Rmin is about 967 Ω and Rmax about 1.77 kΩ. A 1.5 kΩ choice predicts about 254 ns rise time and about 1.93 mA when the low node is at 0.4 V. These are idealized nominal calculations, not certification: resistor tolerance, capacitance spread, device timing, and active-pullup behavior still matter.

Recognize an Impossible Passive Window

Keep the same 3.3 V, 0.4 V, 3 mA, and 300 ns assumptions but increase bus capacitance to 400 pF. The maximum resistance drops to about 885 Ω, below the 967 Ω minimum. No single passive pull-up meets both simplified limits. Choosing 910 Ω by habit still misses at least one bound. Reduce capacitance or speed, separate the bus with a suitable buffer, or choose parts and a topology whose full electrical specifications permit the design. A mode name alone does not guarantee an alternate pull-up method is supported.

Two existing 4.7 kΩ pull-ups in parallel produce 2.35 kΩ, not 4.7 kΩ. At 200 pF the simple rise-time estimate becomes about 398 ns, slower than the 300 ns example limit. If more boards are added, the resistance may fall while capacitance rises; one effect can improve rise time while the other worsens it. Inventory the complete assembled configuration rather than measuring one module alone.

Check Logic Levels and Voltage Domains

The pull-up rail must be safe for every connected pin in all power states. Verify VIH and VIL margins, VOL at the calculated sink current, leakage, absolute-maximum pin voltage, and powered-off back-powering. A bidirectional translator is not a generic resistor divider: it introduces domain-specific pull-ups, capacitance, VOL degradation, direction behavior, and timing delays. The Logic Level Compatibility Calculator supports threshold checks, while the Logic-Level Interfacing Guide covers translation and power sequencing. Neither replaces the selected translator's application circuit.

Clock Stretching and Real Transaction Time

A target may hold SCL low to defer the next clock when supported by the controller and target. Pull-up sizing still determines the released SCL edge, but clock stretching changes the transaction duration and may trigger firmware or hardware timeouts. Check whether the controller truly honors stretching, what maximum low interval it allows, and how a stuck-low fault is recovered. Not every I²C-compatible bridge or peripheral implements stretching the same way.

Do not estimate useful throughput as only clock frequency divided by eight. Address, R/W bit, acknowledge bits, start/repeated-start, stop, command bytes, and stretching all consume time. At 400 kHz, a 9-clock byte interval is at least 22.5 µs of clocking before any setup, stop, stretch, or firmware delay. A ten-byte payload therefore needs more than 200 µs even before the address and control overhead. Measure the actual transaction waveform and useful payload rate.

Bench Validation

Use a low-capacitance probe and state its contribution. A logic analyzer decodes transactions but may not reveal a slow edge hovering near VIH, VOL overdrive, or ringing. Repeat at voltage and temperature corners and with every intended node installed. For unexplained NACKs, distinguish electrical thresholds from address, protocol, and firmware faults.

Common Mistakes

• Copying 4.7 kΩ without estimating Cbus.
• Ignoring parallel pull-ups on plug-in modules.
• Checking rise time but not low-state sink current.
• Using a nominal current limit instead of a guaranteed device limit.
• Assuming one resistance value works for SDA and SCL despite different loads.
• Choosing a resistor even when Rmin exceeds Rmax.
• Ignoring translator capacitance and VOL shift.
• Assuming every controller supports clock stretching.
• Estimating throughput from clock frequency alone.
• Using a logic-analyzer decode as proof of analog margins.
• Forgetting probe capacitance when measuring a marginal bus.
• Assuming all devices are safe at the pull-up voltage when unpowered.

Primary Engineering Sources

Use the current NXP I²C-bus specification and user manual for mode-specific electrical and timing limits, and TI I²C advanced-topic guidance for pull-up, stretching, arbitration, and translation context. Datasheets of every connected device remain authoritative for guaranteed pin limits.