Engineering Guide
Power-Rail Decoupling and PDN Design: Target Impedance, Ripple Current, and Anti-Resonance
A decoupling network is a frequency-dependent current-delivery system. Design it from the load transient and allowable rail error, then include the real capacitor bank, current-loop geometry, regulator, planes, package, and measurement setup.
PDN Design Workflow
| Step | Engineering Action | Boundary |
|---|---|---|
| Define the rail disturbance | Record the load-step amplitude, edge rate, duration, repetition, and allowed voltage deviation. | |
| Set the target impedance | Use Ztarget = ΔVallowed/ΔIstep as an initial broadband design ceiling, not a complete regulator model. | |
| Partition the frequency range | Assign regulator control, bulk capacitance, local ceramics, planes, and package capacitance to the bands they can actually support. | |
| Estimate required charge | Use C ≥ ΔIΔt/ΔV for the interval where capacitance must source the transient before another energy path responds. | |
| Select real components | Apply DC-bias, temperature, tolerance, ESR, ESL, ripple-current, voltage, and lifetime derating. | |
| Build the physical network | Minimize mounting-loop inductance and place local decoupling at the load-current loop, not merely near it on the schematic. | |
| Check resonances | Evaluate the complete impedance profile for self-resonance and anti-resonant peaks between unequal capacitor banks and interconnect inductance. | |
| Validate the assembled PDN | Measure load-step droop and impedance with realistic fixtures, probe loops, operating bias, and populated-board conditions. |
Target Impedance and Transient Charge
Formula reference
First-pass rail constraints
Ztarget = ΔVallowed / ΔIstepCmin = ΔI · Δt / ΔVCΔVESR = ΔI · ESRΔVESL = ESL · di/dtVariable definitions
- Separate capacitive, ESR, and ESL portions of the rail deviation
- Use the relevant current edge and support interval
- Include regulator response and board/package paths
- Do not add every droop term blindly if their timing differs
Target impedance is a useful ceiling, not proof that a flat impedance can or should be maintained at every frequency. Regulator output impedance, control-loop crossover, package inductance, and the load spectrum define the real requirement.
Frequency Roles in the Power Network
| Element | Primary Range | Design Role |
|---|---|---|
| Regulator and control loop | Low frequency | Restores average rail voltage; response is bounded by loop bandwidth and stability. |
| Bulk capacitor | Low to mid frequency | Supplies longer transient charge and handles substantial ripple current. |
| Local ceramic bank | Mid to high frequency | Provides low inductance charge close to switching loads. |
| Power and ground planes | High frequency transition | Distributed capacitance and spreading inductance shape the board-level impedance. |
| Package and die capacitance | Highest frequency | Supports edges too fast for board-mounted components to reach effectively. |
| Damping element | Around resonant peaks | Intentional ESR, resistance, or topology can suppress excessive Q and anti-resonance. |
Real Capacitor Bank Impedance
Formula reference
Frequency and thermal checks
XC = 1/(2πfC)Zcap ≈ ESR + j(2πfESL - 1/(2πfC))fSRF = 1/(2π√(ESL · C))PESR ≈ Irms² · ESRVariable definitions
- Use capacitance at operating DC bias and temperature
- Use ESR and ESL for the relevant frequency and mounting
- Parallel branches share current by impedance, not nominal capacitance alone
- Check anti-resonance in the complete assembled network
The Capacitive Reactance Calculator supplies the ideal XC relationship. The Series & Parallel Capacitor Calculator helps size nominal banks. Neither includes mounting inductance, anti-resonance, regulator dynamics, or bias derating.
Anti-Resonance, Damping, and Placement
A mixed-value bank can produce a narrow impedance maximum between branch resonances. Evaluate manufacturer impedance data with extracted or estimated connection inductance. Damping may come from controlled ESR, a dedicated resistor-capacitor branch, regulator output impedance, or a deliberately selected bulk component. Place high-frequency capacitors so their power and return vias close the smallest possible loop at the load pins.
Worked Engineering Examples
Target impedance
A 1.0 V rail allowing 30 mV deviation during a 3 A step has a first-pass target impedance of 10 mΩ.
Transient charge
If 2 A must be supported for 20 µs with at most 40 mV droop, the ideal minimum is 1000 µF before ESR, ESL, bias, tolerance, and regulator response.
ESR step
A 3 A current step through 8 mΩ effective ESR produces an immediate 24 mV component of rail deviation.
ESL step
A 0.5 nH mounting loop exposed to 1 A/ns produces 0.5 V momentarily, showing why loop geometry matters at fast edges.
Ripple heating
A capacitor carrying 1.5 A RMS with 25 mΩ ESR dissipates about 56 mW at the frequency and temperature where that ESR applies.
Bias derating
A ceramic marked 10 µF may provide much less at its operating DC voltage; the biased capacitance belongs in the impedance model.
Parallel bank
Parallel nominal capacitance adds, but unequal mounting inductance prevents ideal current sharing at high frequency.
Anti-resonance
A bulk capacitor and a low-ESR ceramic can create an impedance peak between their resonances; adding more nominal capacitance does not guarantee a lower peak.
Measurement
A load-step test checks time-domain droop, while a calibrated impedance measurement reveals narrow resonant peaks that a slow transient may miss.
Frequency boundary
At frequencies above a mounted capacitor's effective resonance, the connection is inductive and additional remote capacitance cannot repair the local high-frequency loop.
Measurement and Model Boundaries
Time-domain load steps expose droop, ringing, regulator recovery, and probe artifacts. Frequency-domain impedance measurement exposes resonant peaks and damping. Preserve DC bias where possible, calibrate at the fixture reference plane, use low-inductance probes, and compare populated-board measurements with the model. This workflow does not replace control-loop analysis, electromagnetic extraction, package models, or silicon vendor requirements.
Common Mistakes
Related Calculators
Support reference
FAQ
What is PDN target impedance?
It is an initial maximum impedance derived from allowed rail deviation divided by load-current change. It guides broadband design but does not replace regulator-loop and interconnect analysis.
How much decoupling capacitance do I need?
For a defined support interval, ideal capacitance is at least load-current change times duration divided by allowed capacitive droop. Add ESR, ESL, bias, tolerance, and response margins.
Why are both bulk and local capacitors used?
Bulk parts provide charge over longer intervals, while physically local low-inductance parts support faster current changes. Neither covers every frequency decade.
Why does DC bias matter for ceramic capacitors?
Class II ceramic capacitance can fall substantially with applied DC voltage, changing transient droop, resonance, and target-impedance margin.
What causes PDN anti-resonance?
Different capacitor values and their interconnect inductances form coupled resonant networks. Between resonances, branch impedances can combine into a high-Q impedance peak.
Is the capacitor with the lowest ESR always best?
No. Very low ESR reduces local loss but can increase network Q. Controlled damping and the assembled impedance profile matter more than one isolated ESR value.
How does capacitor placement affect decoupling?
Trace, via, plane, and package inductance limit how quickly current reaches the load. Minimize the complete power-ground loop area and connection length.
How is ripple-current heating calculated?
A first estimate is RMS ripple current squared times ESR at the relevant frequency and temperature. Datasheet ratings and thermal conditions still govern acceptability.
What is capacitor self-resonant frequency?
It is where capacitance resonates with effective series inductance. Above it, the mounted component becomes increasingly inductive.
Can I simply parallel more capacitors?
Parallel parts add low-frequency capacitance, but high-frequency sharing and anti-resonance depend on ESR, ESL, value spread, layout, and mounting geometry.
How should a PDN be measured?
Combine calibrated impedance measurement with realistic load-step testing. Use low-inductance probing and preserve operating bias, population, and fixture conditions.
Does this Guide replace a full PDN simulation?
No. Critical rails require regulator models, plane and package extraction, component impedance data, simulation, and measurement across operating corners.
Summary
Start with load-step and rail-error limits, allocate current delivery by frequency, derate the real components, control loop inductance and anti-resonance, then verify both transient response and assembled impedance.